Information storage medium, information recording apparatus, and information reproduction apparatus

ABSTRACT

An information storage medium according to an embodiment of this invention has an area for storing predetermined data modulated according to the (d, k; m, n) modulation rule. The predetermined data includes at least one SYNC code in a predetermined recording unit, and the number of “1”s included in a predetermined number of a series of channel bits at an arbitrary position in the SYNC code is not more than a half the predetermined number.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. application Ser.No. 11/186,968, filed Jul. 22, 2005, and for which priority is claimedunder 35 U.S.C. §120. U.S. application Ser. No. 11/186,968 is adivisional of application Ser. No. 10/234,402, filed Sep. 5, 2002, nowU.S. Pat. No. 6,999,395, and for which priority is claimed under 35U.S.C. §121. This application is based upon and claims the benefit ofpriority under U.S.C §119 from the prior Japanese Patent Application No.2001-276727, filed Sep. 12, 2001. The entire contents of eachapplication listed above is incorporated herein by reference, in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information storage medium thatrecords data containing a SYNC code. The present invention also relatesto an information recording apparatus for recording data containing aSYNC code on an information storage medium. Furthermore, the presentinvention relates to an information reproduction apparatus forreproducing data containing a SYNC code from an information storagemedium.

2. Description of the Related Art

The DVD format specifies the contents of a SYNC code. In thisspecification, there are a total of 32 different SYNC codes. The SYNCcodes are described in Jpn. Pat. Appln. KOKAI Publication No. 7-254239.

In the existing DVD standard, in order to limit the pit length of athree-dimensional pattern or the maximum mark length of a recording mark(the run length of “0”s allocated between neighboring “1”s in channelbit data), source data undergoes a modulation process based on aspecific modulation rule, and the modulated data is recorded on aninformation storage medium. A modulation method is generally expressedby (d, k; m, n), which symbols mean that “m-bits” source data isconverted into data of “n-channel bits”, and a modulated channel bitpattern has a minimum of “d” “0”s run length and a maximum of “k” “0”srun length. That is, the modulated channel bit patterns satisfyconditions that a minimum of “d” pieces of “0”s successively arrangedand a maximum of “k” pieces of “0”s successively arranged. Themodulation method in the existing DVD standard adopts a (2, 10; 8, 16)method (i.e., “d=2”, “k=10”).

In the next-generation DVD, the recording density is to be furtherimproved. Accordingly, low SYNC code detection precision may pose aproblem.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide an informationstorage medium compatible to high-density recording.

An information storage medium according to an embodiment of the presentinvention comprises a management area that stores managementinformation, and a data area that stores predetermined data inpredetermined recording units,

the predetermined data is modulated according to a (d, k; m, n)modulation rule,

the (d, k; m, n) modulation rule modulates m-bit source data inton-channel bit data, so that modulated channel bit patterns satisfyconditions that a minimum of “d” pieces of “0”s successively arrangedand a maximum of “k” pieces of “0”s successively arranged,

the predetermined data includes at least one SYNC code in thepredetermined recording unit, and

the number of “1”s included in a predetermined number of a series ofchannel bits at an arbitrary position in the SYNC code is not more thana half the predetermined number.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 shows an example of SYNC frame data to be stored in aninformation storage medium;

FIG. 2 shows an example of the data structure when a SYNC code isappended to the SYNC frame data, and that of the SYNC code;

FIG. 3 is a block diagram showing a recording system of an informationrecording/reproduction apparatus according to an embodiment of thepresent invention;

FIG. 4 is a block diagram showing a reproduction system of theinformation recording/reproduction apparatus according to an embodimentof the present invention;

FIG. 5 shows an example of the data structure of physical sector data tobe stored in an information storage medium;

FIG. 6 shows an example of the relationship between physical sector dataand ECC blocks;

FIG. 7 shows an example of the relationship between physical sector dataand ECC blocks;

FIG. 8 shows an example of the data structure of an information storagemedium;

FIG. 9 is a block diagram showing the structure of a SYNC codegenerating/appending unit of the information recording/reproductionapparatus according to an embodiment of the present invention;

FIG. 10 is a block diagram showing the structure around a SYNC codeposition detecting unit of the information recording/reproductionapparatus according to an embodiment of the present invention;

FIG. 11 shows the first example of the data structure of a SYNC code;

FIG. 12 shows the second example of the data structure of a SYNC code;

FIG. 13 shows the third example of the data structure of a SYNC code;

FIG. 14 shows the fourth example of the data structure of a SYNC code;

FIG. 15 shows the fifth example of the data structure of a SYNC code;

FIG. 16 shows the sixth example of the data structure of a SYNC code;

FIG. 17 shows the seventh example of the data structure of a SYNC code;

FIG. 18 shows the eighth example of the data structure of a SYNC code;

FIG. 19 shows the ninth example of the data structure of a SYNC code;

FIG. 20 shows the 10th example of the data structure of a SYNC code;

FIG. 21 shows the 11th example of the data structure of a SYNC code;

FIG. 22 shows an example of the bit pattern of a SYNC code;

FIG. 23 shows an example of the allocation relationship between SYNCcodes and modulated SYNC frame data;

FIG. 24 is a view for explaining a method of determining the SYNC frameposition in one physical sector on the basis of the order in which SYNCframe position identification codes in SYNC codes appear;

FIG. 25 is a flow chart for explaining a data conversion process uponadopting the SYNC codes shown in FIGS. 11 and 12;

FIG. 26 is a flow chart for explaining a data conversion process uponadopting the SYNC codes shown in FIGS. 13 to 18;

FIG. 27 is a flow chart for explaining a data conversion process uponreproducing information;

FIG. 28 is a flow chart for explaining a control operation executed whenthe SYNC codes shown in FIGS. 11 and 12 are adopted and access to apredetermined position on an information storage medium is made;

FIG. 29 is a flow chart for explaining a control operation executed whenthe SYNC codes shown in FIGS. 13 to 18 are adopted and access to apredetermined position on an information storage medium is made;

FIG. 30 is a flow chart showing the method of determining a SYNC framein a physical sector on the basis of the order in which a plurality ofSYNC codes appear;

FIG. 31 is a flow chart for explaining the method of detectingabnormality such as tracking errors on the basis of the order in which aplurality of SYNC codes appear;

FIG. 32 is a view for explaining a SYNC code layout method in onephysical sector data;

FIG. 33 is a view for explaining a practical bit pattern correspondingto SYNC codes shown in FIG. 32;

FIG. 34 is a view for explaining condition αrequired for SYNC codes;

FIG. 35 is a view for explaining condition β required for SYNC codes;

FIG. 36 shows a list of SYNC codes shown in FIG. 22;

FIG. 37 shows a list of SYNC codes shown in FIG. 33; and

FIG. 38 is a view showing reproduced signals of an existing DVD andnext-generation DVD, and for explaining problems of the next-generationDVD.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be described hereinafterwith reference to the accompanying drawings.

As methods of further improving the recording density in anext-generation DVD,

1) a method of generally increasing the recording density while d=2 (toshorten the relative channel bit length), and

2) a method of changing the modulation scheme of d=1, and using PRML(Partial Response Maximum Likelihood) in a reproduction circuit areavailable.

Even when either of these methods is adopted, the signal amplitude of areproduced signal from a repetition position of the densest pattern (theresolution representing the amplitude ratio to the signal amplitude at arepetition position of the coarsest pattern) drops considerably. Amethod of improving the reliability of a reproduced signal using theabove PRML technique against a signal amplitude drop of the reproducedsignal from the repetition position of the densest pattern is beingdeveloped currently.

In general, an information reproduction apparatus or informationrecording/reproduction apparatus associated with an information storagemedium such as an optical disk or the like adopts “SYNC detection” uponreproducing data recorded on the information storage medium. “SYNCdetection” is a method of extracting a reference clock (reproducing acarrier) from a signal reproduced from data recorded on an informationstorage medium, and decoding data recorded on the information storagemedium in synchronism with the timing of this reference clock (carrier).Especially, when a signal amplitude drop of a reproduced signal from therepetition position of the densest pattern is considerable, the timingof this reference clock deviates, and data cannot be preciselyreproduced even using the PRML technique.

In the existing DVD standard, SYNC codes are inserted at specific dataintervals. Upon reproducing information from an information storagemedium, an information reproduction apparatus or informationrecording/reproduction apparatus detects the insertion position of eachSYNC code, and extracts a gap position of data contiguously recorded onthe information storage medium with reference to this SYNC code.Especially, this SYNC code has no error correction code unlike ingeneral user data (SYNC frame data 105 in FIG. 1). Therefore, theinformation reproduction apparatus or information recording/reproductionapparatus is required to have very high detection precision of SYNCcodes.

In order to further improve the recording density in the next-generationDVD, the detection precision of SYNC codes lowers considerably since thetiming of a reference clock deviates (bit shift occurs) near therepetition position of the densest pattern in a SYNC code. FIG. 38 showssuch state. In FIG. 38, the upper reproduced signal indicates that ofthe existing DVD, and the lower reproduced signal indicates that of thenext-generation DVD. In the next-generation DVD, the densestamplitude/coarsest amplitude=Imin/Imax≦0.15. In the reproduced signal ofthe next-generation DVD, if the densest amplitude is small and asymmetryis poor, the timing of a reference clock of a reference clock generationcircuit deviates and a bit shift may occur due to binarization errors ina Schmitt trigger circuit and PLL errors in a PLL circuit.

Features of the present invention will be summarized first.

As a pattern for a SYNC code that can assure high detection precision ofthe SYNC code even when the recording density of an information storagemedium is improved, the number of times of repetition of the densestpatterns in the SYNC code is limited, or a generation state of a patternapproximate to the densest pattern is constrained.

As a result (of the above device of the SYNC code pattern), the range ofthe amplitude value of a reproduced signal from the SYNC code isbroadened, the reference clock extraction (carrier reproduction)precision by “SYNC detection” using a reproduced signal from the SYNCcode position is improved, and the frequency of occurrence of timingdeviation (bit shift) of a reference clock at the SYNC code position isdecreased, thereby improving the detection precision of the SYNC code.

The SYNC code pattern in the present invention has the followingfeatures.

(1-1) A condition for limiting the number of times of repetition of thedensest patterns from every SYNC code patterns, or for constraining thegeneration state of a pattern approximate to the densest pattern is set.

(1-2) The ratio of SYNC code patterns that meet the above condition tosets of SYNC code patterns to be used in practice is increased (set at aspecific occupation ratio or higher).

(1-3) As a condition setting method of the SYNC code pattern, a specificcondition is applied to the frequency of occurrence of “1” within therange of a specific channel bit length N (indicating the bit boundaryposition of a three-dimensional pattern or the mark edge position of arecording mark when a mark length recording method based on an NRZI (NonReturn to Zero Invert) method is used).

(1-4) As a condition setting method of the SYNC code pattern, the“condition of (1-3)” is met everywhere in a SYNC code data area.

As shown in FIGS. 22, 33, 34, and 35, the data size of a SYNC code in anembodiment of the present invention is 24 or 32 channel bits. If thecondition is set for every data size (24 or 32 channel bits) of the SYNCcode, the following problems are posed.

(2-1) Since the condition must be set for every SYNC codes, thecondition to be set becomes complicated.

(2-2) Pattern matching for all patterns is required, and it becomestroublesome to check if the condition is met.

(2-3) If the data size of the SYNC code has changed, the condition mustbe changed. Hence, versatility upon changing the data size of a SYNCcode or a modulation method becomes poor.

By contrast, if it is determined in the present invention that adiscrimination unit (1 channel byte or more) smaller than the data size(24 or 32 channel bits) unit of a SYNC code is set, and the condition ismet everywhere in the SYNC code area as in (1-3) and (1-4) above, thefollowing effects are obtained.

(3-1) The condition to be set for the SYNC code can be greatlysimplified.

(3-2) Since the condition to be set is simple, it becomes very easy tocheck if the condition is met.

(3-3) High condition versatility that is hardly influenced even when thedata size of the SYNC code or the modulation method has changed can beassured.

Many information recording/reproduction apparatuses or informationreproduction apparatuses execute data processes for respective bytes (8bits). Therefore, at least 8 channel bits are required as the “specificchannel bit length” that designates the range in the condition of (3-3)(in the present invention, modulated bits are expressed as channelbits). The present invention will define a method of setting the“specific channel bit length” to have “8+1” channel bits as a startingpoint in consideration of a slight margin for 8 channel bits so that thecondition of the present invention can be applied even when the d valueor various states have changed upon modulation.

When d=1, a repetition pattern of the densest patterns within a channelbit range of 8 channel bits or more requires 9 channel bits, i.e.,“101010101”, as shown in portion (a) in FIG. 34, and after a d+1 (=2)channel bit pattern repeats itself four times, “1” is inserted. On theother hand, when d=2, 10 channel bits, i.e., “1001001001”, are required,as shown in portion (b) in FIG. 34, and after a d+1 (=3) channel bitpattern repeats itself three times, “1” is inserted.

A characteristic feature of the present invention lies in that the valueof the “specific channel bit length N” is designated by the number ofchannel bits obtained by adding one channel bit required to insert “1”at the end of the pattern to a repetition pattern of the densestpatterns of 8 channel bits or more. Irrespective of the d value thatrepresents the “0” run length in the densest pattern after modulation(by providing versatility independently of the modulation method), thenumber of times of repetition of the densest patterns equal to or largerthan 8 channel bits is given, to have “8+1” channel bits as the startingpoint, by:INT[9/(d+1)]  (1)where INT[X] is an integer obtained by dropping digits after the decimalpoint of real number X. Since the number of channel bits for one periodof the densest pattern is “d+1”, the number of channel bits obtainedupon repetition by the number of times given by formula (1) is given by:(d+1)×INT[9/(d+1)]  (2)Since the number of channel bits obtained by adding 1 channel bitrequired to insert “1” at the end of the pattern to formula (2)corresponds to the “specific channel bit length N”, the specific channelbit length N indicating the range for designating the constraintcondition of the SYNC code is given by:N=(d+1)×INT[9/(d+1)]+1  (3)As shown in FIG. 34, from equation (3), we have:N=9 channel bits when d=1N=10 channel bits when d=2

As the constraint condition of the SYNC code pattern, the presentinvention defines “condition α” as a condition that excludes patterns inwhich the first and last bits in N channel bits are “1”, and all bitsbetween these bits are repetition of densest patterns. In a pattern ofN=9 channel bits from the head shown in portion (a) in FIG. 34, sincethe number of channel bits of a repetition pattern of one densestpattern is d+1 channel bits, the number of “1”s in N channel bits isgiven by:INT[N/(d+1)]+1=5  (4)Hence, if “condition α” is expressed by a numerical value, the number of“1”s included in N channel bits can be limited to not more than:INT[N/(d+1)]  (5)When d=1, since the pattern in portion (a) in FIG. 34 includes five “1”swithin N=9 channel bits, it does not meet “condition α”, and is notsuitable for a SYNC code pattern in the present invention. A patternshown in portion (c) in FIG. 34 meets “condition α”, and can be used asa SYNC code pattern of the present invention, since there are four “1”s(INT[N/(d+1)]=4) within N=9 channel bits. Likewise, when d=2,INT[N/(d+1)]=3. A pattern in portion (b) in FIG. 34 does not meet“condition α”, and a pattern in portion (d) in FIG. 34 meets “conditionα”. The existing DVD standard adopts a pattern in portion (b) in FIG. 34as a part of a SYNC code. At the recording density of the existing DVD,a SYNC pattern can be detected without any problem if “condition α” isnot met. A characteristic feature of the present invention lies in thatthe SYNC pattern detection precision is improved by excluding patternswhich do not meet “condition α” from the SYNC codes when the recordingdensity is to be further improved as in the present invention.

When the recording density on an information storage medium has beenimproved, signal detection must be done using the PRML method that usesa PR equalization circuit 130 and Viterbi decoder 156 of arecording/reproduction apparatus shown in FIGS. 3 and 4. When PRML isused, an effect of setting a higher density is expected upon adoptingthe modulation method of d=1 rather than that of d=2. Therefore,especially in respective conditions, those for d=1 will be explained inmore detail. That is, in “condition α” of the present invention, whend=1, “the number of “1”s must be set to be 4 or less within 9 channelbits”.

“Condition α” constrains the repetition pattern of the densest patterns.In the present invention, “condition β” and “condition γ” are used tolimit the ratio of adopting patterns approximate to repetition of thedensest patterns. “Condition β” and “condition γ” are set by slightlymoderating equation (3) and formula (5).

That is, in “condition β” of the present invention, the number of “1”swithin an area of continuous N−1 channel bits is limited to not morethan:INT[(N−1)/(d+1)]  (6)

Under this condition,

the number of “1”s within 8 channel bits is limited to 3 or less whend=1, and

the number of “1”s within 9 channel bits is limited to 2 or less whend=2.

Portions (a) and (b) in FIG. 35 show patterns which do not meet“condition β”, and portions (c) and (d) in FIG. 35 show patterns whichmeet “condition β”. In the existing DVD, the ratio of patterns whichmeet “condition β” to all patterns adopted as SYNC codes is as low as65.6%. In order to improve the density to be higher than that of theexisting DVD and to improve the SYNC code detection precision, a largecharacteristic feature of the present invention lies in that the ratioof adopting patterns that meet “condition β” is set to be at least 66%.In order to further improve the SYNC code detection precision,preferably, the ratio of adopting patterns that meet “condition β” mustbe set to be 75% or higher.

In “condition γ” of the present invention, the number of “1”s within 7channel bits is limited to 3 or less, and 75% or more of all SYNC codepatterns are set to be patterns which meet “condition γ”.

FIGS. 22, 33, 36, and 37 show embodiments of SYNC code patterns whichare set in consideration of the above conditions.

The pattern of a SYNC position detection code 121 shown in FIGS. 22 and33 has the following features.

1) The spacing between neighboring “1”s is larger than the maximumlength that can be generated by a modulation rule (in this example,“k+3” “0”s run, or “k+3” pieces of “0”s run).

2) All patterns meet condition α.

3) 66% or more patterns of all patterns meet condition β.

Pattern P1 shown in FIG. 36 does not conform to “condition γ”. Allpatterns shown in FIG. 36 meet “condition α” and “condition β”.

Pattern P1 shown in FIG. 37 does not conform to “condition γ”, andpattern P2 does not conform to “condition β”. All patterns shown in FIG.36 meet “condition α”.

FIGS. 22 and 36 show an identical pattern using different indicationmethods. The occupation ratio of patterns which meet “condition β” is94%, and that of patterns which meet “condition γ” is 97%. In FIG. 36, apattern which does not meet “condition γ” i-s indicated as pattern P1.

FIGS. 33 and 37 show an identical pattern using different indicationmethods. The occupation ratio of patterns which meet “condition β1” isas high as 100%, and that of patterns which meet “condition γ” is ashigh as 96%. In FIG. 37, a pattern which does not meet “condition γ” isindicated as pattern P1, and a pattern which does not meet “condition β”is indicated as pattern P2.

An information storage medium on which the aforementioned SYNC codepatterns are recorded, and an information recording/reproductionapparatus for recording the SYNC code patterns on an information storagemedium, and reproducing the SYNC code patterns from the informationstorage medium will be described below.

FIGS. 1 and 2 are views for explaining the data structure recorded on aninformation storage medium of the present invention.

Portion a in FIG. 1 indicates a pack sequence which includes a videopack 101 a, audio pack 102 a, . . . and portion b indicates logicalsector information (103-0, 103-1, 103-2, . . . ) corresponding to eachpack. Also, portion c indicates a state wherein one logical sectorinformation 103-0 is scrambled, and PI information is appended to eachrow (each of 12 rows in this example). Furthermore, Data ID, IED, andCPR_MAI are appended to the first row. The last row (13th row) of thislogical sector information stores PO information.

A sector block (for 13 rows) shown in portion c in FIG. 1 is segmentedinto SYNC frame data 105-0, 105-1, . . . (a total of 26 (13×2) data). ASYNC code (to be described later) is appended between neighboring SYNCframe data. That is, a SYNC code is appended to the head of each SYNCframe data.

FIG. 2 shows a state wherein SYNC codes are inserted between neighboringSYNC frame data, as indicated by portions of symbols d and f. Each SYNCcode is made up of a variable code field 112 and fixed code field 111,as in portion f, and these fields have contents, as shown in portionsindicated by symbols g and h in FIG. 2.

A characteristic arrangement will be explained below.

Video information is recorded on an information storage medium 9 in theform of 2048-byte video packs 101 and audio packs 102 (portion a), asshown in FIG. 1. This 2048-byte recording unit is handled as logicalsector information 103 (portion b).

In the existing DVD standard, data obtained by appending Data ID 1-0,IED 2-0, and CPR_MAI 18-0 to this data, and PI (Parity of Inner-code)information and PO (Parity of Outer-code) information corresponding toan ECC structure shown in FIGS. 5 to 7 is segmented to form 26 equalSYNC frame data 105-0 to 105-25 (portions of symbol d in FIGS. 1 and 2).In this case, PO information is also segmented into two equal data.

The respective SYNC frame data 105 are modulated, and SYNC codes 110 ofthe present invention are inserted between neighboring modulated SYNCframe data 106. A modulation method is generally expressed by (d, k; m,n), which symbols mean that “m-bit” source data is converted into“n-channel bits”, and a modulated channel bit pattern has a minimum of“d” “0”s run length and a maximum of “k” “0”s run length. That is, themodulated channel bit patterns satisfy conditions that a minimum of “d”pieces of “0”s successively arranged and a maximum of “k” pieces of “0”ssuccessively arranged.

An embodiment of the present invention adopts a modulation methoddescribed in, e.g., “Jpn. Pat. Appln. KOKAI Publication No.2000-332613”. In this modulation method,d=1,k=9,m=4,n=6Each SYNC code 110 is segmented into a fixed code field 111 and variablecode field 112, and has a structure in which a “pattern 129 whichintegrally serves as a conversion table selection code upon modulation,SYNC frame position identification code, and DC suppression polarityinversion pattern” is allocated in the variable code field 112, and aSYNC position detection code 121 is allocated in the fixed code field111. In the following description, reference numerals are assigned tothese codes and pattern to refer to them as a conversion table selectioncode 122 upon modulation, SYNC frame position identification code 123,and DC suppression polarity inversion pattern 124, processes of whichwill be described independently. However, since these codes and patternare integrally allocated in the variable code field 112, they areprocessed together.

Note that modulation herein means conversion of input data intomodulated data according to the aforementioned modulation rule. In thiscase, this conversion process adopts a method of selecting modulateddata corresponding to input data from a large number of modulated datastored in conversion tables. Therefore, information indicating a tableused to convert into modulated data upon modulation is necessary, andthis information is the “conversion table selection code 122 uponmodulation”, which represents a conversion table used to generate thenext modulated data to that immediately after a SYNC code.

The “SYNC frame position identification code 123” is used to identifythe frame position of the SYNC frame in a physical sector. A frame canbe identified by the layout pattern of a plurality of SYNC frameposition identification codes before and after the frame of interest.

A large characteristic feature of the present invention lies in that thepractical contents of the SYNC position detection code 121 are formed bya combination of a pattern in which “k+3” “0”s run, and a pattern inwhich two “0”s run, as shown in portion h in FIG. 2. In order tofacilitate position detection of each SYNC code 110, a code which neverexists in the modulated SYNC frame data 106 is allocated in the SYNCposition detection cod 121.

Since the modulated SYNC frame data 106 has been modulated according tothe (d, k; m, n) modulation rule, “k+1” “0”s never run in the modulateddata. Therefore, it is desirable to allocate a pattern in which “k+1” ormore “0”s run as a pattern in the SYNC position detection code 121.

However, when the pattern in which “k+1” “0”s run is allocated as thepattern in the SYNC position detection code 121, if a plurality of bitshift errors occur upon reproducing modulated SYNC frame data 106, sucherrors may be erroneously detected as the SYNC position detection code121. Therefore, a pattern in which “k+2” or more “0”s run is preferablyallocated as a pattern in the SYNC position detection code 121. However,if the “0” run pattern is too long, a phase error readily occurs in aPLL circuit 174.

The existing DVD adopts a pattern in which “k+3” “0”s run (themodulation rule of the existing DVD is (2, 10; 8, 16)). Therefore, inorder to suppress generation of bit shift errors and to assurereliability of the position detection of the SYNC code 110 andinformation reproduction compared to the existing DVD, the run length of“0”s must be set to be “k+3” or less.

As described in “Jpn. Pat. Publication No. 10-275358”, a DSV (DigitalSum Value) value changes depending on a modulated bit pattern. If theDSV value largely deviates from 0, it can approach 0 by changing a bitfrom “0” to “1” at an optimal bit pattern position.

In this way, in the present invention, the SYNC code 110 includes a DCsuppression polarity inversion pattern 124 having a specific patternwhich makes the DSV value approach 0.

When the modulation method described in “Jpn. Pat. Appln. KOKAIPublication No. 2000-332613” is adopted, 6 channel bits to bedemodulated must be modulated also using “selection information of aconversion table used upon modulation of 6-channel bit modulated data”,which is present immediately after 6-channel bit modulated data to bedemodulated.

Therefore, as shown in portion e in FIG. 2, selection information of aconversion table for 6 channel bits which should appear after the last6-channel bit data of the modulated SYNC frame data 106 allocatedimmediately before the SYNC code 110 is recorded in the conversion tableselection code 122 upon modulation in the SYNC code 110. That is, theSYNC code 110 includes the conversion table selection code 122 uponmodulation. This conversion table selection code 122 upon modulation isconversion table selection information for 6-channel bit data whichshould appear after the last 6-channel bit data of the immediatelypreceding SYNC frame data 106. By looking up this conversion table data,a conversion table to be used upon demodulating the next data can bedetermined.

FIGS. 3 and 4 show the structure of an informationrecording/reproduction apparatus according to the present invention.

FIG. 3 shows a recording system, and FIG. 4 shows a reproduction system.A controller 143 controls the overall apparatus. A Data ID, IED,CPR_MAI, EDC appending unit 168 appends Data ID, IED, CPR_MAI, and EDCto logical sector information 103 input from an interface 142. The DataID is generated by a Data ID generator 165 on the basis of apredetermined rule. The CPR_MAI is output from a CPR_MAI generator 167.The logical sector information 103 appended with the Data ID, IED,CPR_MAI, and EDC is input to a scramble circuit 157, and the entire datais scrambled. The scrambled data is input to an ECC encoding circuit161, and is converted into ECC blocks. The ECC blocks are shown inportions indicated by symbols h and i in FIG. 6.

The ECC blocks are input to a modulation circuit 151 and are modulated.This modulation process uses a conversion table in a conversion tablememory 153 (e.g., a conversion table from 4 bits into 6 bits). Uponselecting modulated data from a table, a DSV calculator 148 calculates aDSV of continuous modulated data, and modulated data is selected so thatDC components fall within a predetermined level range (0 or 1 run lengthfalls within a predetermined value range). A DC suppression polarityinversion pattern is selected in accordance with the DSV calculationresult. A SYNC frame position identification code generator 136 outputsa SYNC frame position identification code. The SYNC frame positionidentification code is used to identify a frame in one ECC block.

The modulated data (SYNC frame data) and modulation related information(SYNC code: the conversion table selection code, the SYNC frame positionidentification code, information used to select the DC suppressionpolarity inversion pattern, and the like) are stored in a temporarymemory 150, and are then supplied to a SYNC code generating/appendingunit 146. The SYNC code generating/appending unit 146 appends a codeshown in portion h in FIG. 2 in the SYNC code. That is, the SYNC codegenerating/appending unit 146 generates and appends a SYNC code patternas the aforementioned characteristic feature of the present invention.

The detailed contents of the temporary memory 150 of modulated data andmodulation related information, and the SYNC code generating/appendingunit 146 are shown in FIG. 9 (to be described later).

The data converted into SYNC frames are supplied to an informationrecording/reproducing unit 141, and are recorded on an optical disk.

Data reproduced from the optical disk undergoes waveform equalizationfrom the information recording/reproducing unit 141 to a PR equalizationcircuit 130, and is then converted into digital data by an A/D converter169. The digital data is input to a code position extractor 145 andshift register circuit 170 via a Viterbi decoder 156. Modulated data inthe shift register circuit 170 is input to a demodulation circuit 152 inaccordance with the SYNC position extraction result of the code positionextractor 145, and is demodulated using a conversion table in ademodulation conversion table memory 154 (e.g., a conversion table from6 bits into 4 bits). From the demodulated data, a Data ID field & IEDfield extractor 171 extracts Data ID and IED. The Data ID undergoeserror checking by a Data ID field error checker 172 using the IED. If noerror is found, it is determined that ECC blocks are normallyreproduced. If any error is found, for example, ECC blocks are readagain.

ECC blocks are input to an ECC decoding circuit 162 to undergo an errorcorrection process. The error-corrected data are descrambled by adescramble circuit 159 to obtain original logical sector information,which is extracted by a logical sector extractor 173. The extractedlogical sector is sent to a data decode processor (not shown) via theinterface 142.

FIGS. 5, 6, and 7 show processes in which ECC blocks are formed based onthe data sequence shown in portion c in FIG. 1. Portion d in FIG. 5describes respective rows of an ECC block as data 0-0-0, 0-0-1, 0-0-2, .. . . Physical sector data forms 13 rows of frames. PI information isappended to each row of this physical sector, and the last rowcorresponds to that of PO information. One ECC block is formed by aplurality of physical sector data. PO information is generated for eachECC block formed by a plurality of physical sectors, and is distributedto every rows of physical sectors.

As shown in FIG. 7, every other physical sector data are selected andare distributed to first and second small ECC blocks 7-0 and 7-1.

In this example, one of physical sector data (portion f) consists of 13rows. One of these rows is a portion of PO information. One small ECCblock is formed by 31 physical sector data. Sixty-two physical sectordata (two small ECC blocks) are divided into, e.g., even and odd sectordata, thus generating PO information for each of a block formed by theeven sector data, and that defined formed by the odd sector data.

FIG. 7 shows allocation of physical sector data and the relationshipbetween the physical sector data, which are allocated in this way, andECC blocks. FIG. 8 shows a state wherein physical sector data are laidout on the information storage medium 9. First and second small ECCblocks are formed by fetching every other physical sector data allocatedon a track. As shown in FIG. 8, the information storage medium 9comprises a management area 9 a and data area 9 b. The management area 9a is used to store management information. The management area 9 a isalso called a lead-in or lead-out area, and is assured on, e.g., theinnermost or outermost periphery of the information storage medium 9.The management information includes, e.g., defect management informationor the like. On the other hand, the data area 9 b is used to storepredetermined data. The predetermined data includes, e.g., user data.

In the embodiment of the present invention, the channel bit interval isshortened nearly to the limit by aiming at a higher recording density ofthe information storage medium 9. As a result, when a pattern“101010101010101010101010” as repetition of a pattern of d=1 is recordedon the information storage medium 9, and that data is reproduced by theinformation recording/reproducing unit 141, it is close to the cutofffrequency of MTF characteristics of a reproduction optical system. Forthis reason, most of the signal amplitude of a reproduced signal isburied in noise.

As a method of reproducing recording marks or pits, the spacings ofwhich are shortened nearly to the limit (cutoff frequency) of the MTFcharacteristics to attain a higher density, the embodiment of thepresent invention adopts a PRML technique. That is, a signal reproducedfrom the information recording/reproducing unit 141 undergoesreproduction waveform correction by the PR equalization circuit 130. TheA/D (analog-to-digital) converter 169 samples the signals that haspassed through the PR equalization circuit 130 in synchronism with thetiming of a reference clock 198 sent from a reference clock generationcircuit 160, thus converting the signal into digital data, and thedigital data undergoes a Viterbi decoding process in the Viterbi decoder156.

The data that has undergone the Viterbi decoding process is processed inthe same manner as conventional data which has been binarized based on aslice level. Upon adopting the PRML technique, if the sampling timing ofthe A/D converter 169 deviates, the error rate of data after Viterbidecoding increases. Hence, in order to improve the precision of thesampling timing, the information reproduction apparatus or informationrecording/reproduction apparatus of the present invention independentlyhas a special sampling timing extraction circuit (a combination of theSchmitt trigger binarization circuit 155 and the PLL circuit 174).

The information reproduction apparatus or informationrecording/reproduction apparatus of the present invention ischaracterized in that the Schmitt trigger binarization circuit 155 isused as a binarization circuit. This Schmitt trigger binarizationcircuit 155 has characteristics in that a specific width (in practice, aforward voltage value of a diode) is provided to a binarization slicereference level, and binarization is one only when that specific widthhas been exceeded. Therefore, when the aforementioned pattern“101010101010101010101010” is input, since the signal amplitude is verysmall, no binarization switching takes place. When a pattern coarserthan this pattern, e.g., “1001001001001001001001” is input, theamplitude of a reproduced signal increases. Therefore, polarityswitching of an output binary signal occurs in synchronism with thetiming of “1” in the Schmitt trigger binarization circuit 155. Theembodiment of the present invention adopts the NRZI (Non Return to ZeroInvert) method, and the “1” positions of the pattern match the edges(boundaries) of the recording marks or pits.

The PLL circuit 174 detects frequency and phase errors between a binarysignal as the output from the Schmitt trigger binarization circuit 155,and the reference clock signal 198 sent from the reference clockgeneration circuit 160, and changes the frequency and phase of itsoutput clock. The reference clock generation circuit 160 feeds back (thefrequency and phase of) the reference clock 198 to reduce the error rateafter Viterbi decoding using the output signal from the PLL circuit 174,and decoding characteristic information of the Viterbi decoder 156 (morespecifically, information of the convergence length (distance requireduntil convergence) in a path metric memory (not shown) in the Viterbidecoder 156).

The ECC encoding circuit 161, ECC decoding circuit 162, scramble circuit157, and descramble circuit 159 in FIG. 2 execute 1-byte processes. If1-byte data before modulation is modulated according to the (d, k; m, n)modulation rule, the length after modulation is given by:8n/m  (11)

Therefore, when the data processing unit in each of the above circuitsis converted into a processing unit after modulation, it is given byformula (11). Since the processing unit of the modulated SYNC frame data106 in portion e in FIG. 2 is given by formula (11), the data size(channel bit size) of the SYNC code 110 must be set to be an integermultiple of formula (11) for the purpose of achieving integration ofprocesses between the SYNC code 110 and modulated SYNC frame data 106shown in portion e in FIG. 2.

Therefore, a large characteristic feature of the present invention liesin that integration of processes between the SYNC code 110 and modulatedSYNC frame data 106 is assured by setting the size of the SYNC code 110in the embodiment of the present invention by:8Nn/m  (12)where N is an integer value.

As an embodiment of the present invention, since an explanation has beengiven so far under the condition thatd=1,k=9,m=4,n=6if these values are substituted in formula (12), the total data size ofthe SYNC code 110 is:12N  (13)

FIG. 9 shows details of a block (SYNC code generating/appending unit146) for generating a SYNC code 110 according to the present invention,and for appending this SYNC code to a SYNC frame to generate a data unitto be recorded, and the temporary memory 150 of modulated data andmodulation related information. The operations of these blocks will bedescribed later with reference to the flow chart.

FIG. 10 shows details of the code position extractor 145 anddemodulation circuit 152. The operations of these blocks will bedescribed later with reference to the flow chart.

FIGS. 11 to 21 show the structure in a SYNC code in the presentinvention.

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 11, aconversion table selection code 122 upon modulation and SYNC positiondetection code 121 are allocated as SYNC information (SY), and a DCsuppression polarity inversion pattern 124 and SYNC frame positionidentification code 123 are allocated in turn as frame information (FR).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 11, aconversion table selection code 122 upon modulation, DC suppressionpolarity inversion pattern 124, and SYNC position detection code 121 areallocated as SYNC information (SY), and a SYNC frame positionidentification code 123 is allocated as frame information (FR).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 12, aconversion table selection code 122 upon modulation and SYNC frameposition identification code 123 are allocated in turn as frameinformation (FR), and a SYNC position detection code 121 and DCsuppression polarity inversion pattern 124 are allocated in turn as SYNCinformation (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 12, aconversion table selection code 122 upon modulation, DC suppressionpolarity inversion pattern 124, and SYNC frame position identificationcode 123 are allocated in turn as frame information (FR), and a SYNCposition detection code 121 is allocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (C) in FIG. 12, aconversion table selection code 122 upon modulation, SYNC frame positionidentification code 123, DC suppression polarity inversion pattern 124,and SYNC frame position identification code 123 are allocated in turn asframe information (FR), and a SYNC position detection code 121 isallocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 13, aconversion table selection code 122 upon modulation and SYNC positiondetection code 121 are allocated as SYNC information (SY), and a patternthat integrates a SYNC frame position identification code 123 and DCsuppression polarity inversion pattern 124 is allocated as frameinformation (FR).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 13, apattern that integrates a conversion table selection code 122 uponmodulation and DC suppression polarity inversion pattern 124, and a SYNCposition detection code 121 are allocated as SYNC information (SY), anda SYNC frame position identification code 123 is allocated as frameinformation (FR).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 14, apattern that integrates a conversion table selection code 122 uponmodulation and SYNC frame position identification code 123 is allocatedas frame information (FR), and SYNC position detection code 121 and DCsuppression polarity inversion pattern 124 are allocated as SYNCinformation (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 14, apattern that integrates a conversion table selection code 122 uponmodulation and DC suppression polarity inversion pattern 124, and a SYNCframe position identification code 123 are allocated as frameinformation (FR), and a SYNC position detection code 121 is allocated asSYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 15, apattern that integrates a conversion table selection code 122 uponmodulation and SYNC frame position identification code 123, and DCsuppression polarity inversion pattern 124 are allocated as frameinformation (FR), and a SYNC position detection code 121 is allocated asSYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 15, aconversion table selection code 122 upon modulation and a pattern thatintegrates a SYNC frame position identification code 123 and DCsuppression polarity inversion pattern 124 are allocated in turn asframe information (FR), and a SYNC position detection code 121 isallocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 16, apattern that integrates a conversion table selection code 122 uponmodulation, SYNC frame position identification code 123, and DCsuppression polarity inversion pattern 124 is allocated as frameinformation (FR), and a SYNC position detection code 121 is allocated asSYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 16, apattern that integrates a conversion table selection code 122 uponmodulation, SYNC frame position identification code 123, DC suppressionpolarity inversion pattern 124, and SYNC position detection code 121 isallocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 17, apattern that integrates a conversion table selection code 122 uponmodulation and SYNC frame position identification code 123 is allocatedas frame information (FR), and a pattern that integrates a SYNC positiondetection code 121 and DC suppression polarity inversion pattern 124 isallocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 17, aconversion table selection code 122 upon modulation and SYNC frameposition identification code 123 are allocated as frame information(FR), and a pattern that integrates a SYNC position detection code 121and DC suppression polarity inversion pattern 124 is allocated as SYNCinformation (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 18, aconversion table selection code 122 upon modulation and DC suppressionpolarity inversion pattern 124, and a pattern that integrates a SYNCposition detection code 121 and SYNC frame position identification code123 are allocated in turn as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 18, aconversion table selection code 122 upon modulation, and a pattern thatintegrates a SYNC position detection code, SYNC frame positionidentification code, and DC suppression polarity inversion pattern areallocated as SYNC information (SY).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 19, aconversion table selection code 122 upon modulation, SYNC positiondetection code 121, and DC suppression polarity inversion pattern 124are allocated in turn as SYNC information (SY), and a modulated SYNCframe position identification code 125 is allocated as frame information(FR).

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 19, aconversion table selection code 122 upon modulation, DC suppressionpolarity inversion pattern 124, and SYNC position detection code 121 areallocated in turn as SYNC information (SY), and a modulated SYNC frameposition identification code 125 is allocated as frame information (FR).

In a SYNC code 110 of an embodiment shown in FIG. 20, a pattern thatintegrates a conversion table selection code 122 upon modulation and DCsuppression polarity inversion pattern 124 is allocated as SYNCinformation (SY), and a modulated SYNC frame position identificationcode 125 is then allocated as frame information (FR).

In a SYNC code 110 of an embodiment shown in portion (A) in FIG. 21,SYNC information (SY) alone is stored, i.e., a conversion tableselection code 122 upon modulation, SYNC position detection code 121,and DC suppression polarity inversion pattern 124 are allocated in turn.

In a SYNC code 110 of an embodiment shown in portion (B) in FIG. 21,SYNC information (SY) alone is stored, i.e., a conversion tableselection code 122 upon modulation, DC suppression polarity inversionpattern 124, and SYNC position detection code 121 are allocated in turn.

In a SYNC code 110 of an embodiment shown in portion (C) in FIG. 21,SYNC information (SY) alone is stored, i.e., a pattern that integrates aconversion table selection code 122 upon modulation and DC suppressionpolarity inversion pattern 124, and a SYNC position detection code 121are allocated in turn.

As described above, according to the present invention, differentallocation structures of a conversion table selection code 122 uponmodulation, SYNC position detection code 121, SYNC frame positionidentification code 123, and DC suppression polarity inversion pattern124 are available as examples of a SYNC code 110 without coming usingthem.

In addition, structures that combine or commonly use some of thosestructures are available.

FIGS. 19 and 20 show structures in which a modulated SYNC frame positionidentification code 125 is modulated. With such structure, the channelbit size of a non-modulated data field 108 can be reduced to improve theSYNC code detection performance.

FIG. 23 shows various embodiments of a SYNC code allocation method inone physical sector according to the present invention. In b of FIG. 23,a sequence of SYNC codes 110 and modulated SYNC frame data 106, whichare shown in line in portion e of FIG. 2, is rearranged into a matrixpattern for the sake of easy view.

As application examples of the embodiment of the present invention, theinternal structure of a SYNC code can have various structures, as shownin FIGS. 11 to 21. In order to obtain correspondence between thepractical structure in each SYNC code 110 used in FIG. 23, and thestructures shown in FIGS. 11 to 21, respective portions in therespective structures shown in FIGS. 11 to 21 are combined into groups“SY”, “SY*”, and “FR*” (* indicates a numerical value), andcorrespondence between the respective portions and the combined groupsare shown in FIGS. 11 to 21.

In the structure shown in FIG. 23, each SYNC code has an internalstructure shown in one of portion (B) in FIG. 16, portion (A) in FIG.18, and portion (B) in FIG. 18. However, the structure of FIG. 23 hasthe same combination/allocation order of SYNC position numbers 115corresponding to practical SYNC frame position identification codes 123(commonly used as other codes/patterns).

A large characteristic feature of the present invention lies in that notonly “SY0” in FIG. 23 is allocated at the first position in a singlephysical sector, but also identical “SY0” is also allocated at otherpositions (second, fifth, seventh, 14th, 15th, 18th, and 20th). Also,the next characteristic feature lies in that when one physical sector iscompletely segmented into two blocks (segmented into two blocks to havethe last portion of modulated SYNC frame data 106-12 as a boundary), thepositions of “SY0” before and after the boundary of segmentation blockscompletely match.

That is, “SY0” is present immediately before modulated SYNC frame data106-0, and “SY0” is present immediately before modulated SYNC frame data106-13 in correspondence with it. Also, “SY0” is present immediatelybefore modulated SYNC frame data 106-1, and “SY0” is present immediatelybefore modulated SYNC frame data 106-14 in correspondence with it.Furthermore, “SY0” is present immediately before modulated SYNC framedata 106-4, and “SY0” is present immediately before modulated SYNC framedata 106-17 in correspondence with it.

In this way, when one physical sector is segmented into two blocks, and“SY0” is symmetrically allocated before and after the boundary ofsegmentation, if “SY0” is detected at an arbitrary position in aphysical sector, 26 different ranges from which the position ofmodulated SYNC frame data 106 is to be detected in the conventionalmethod can be halved to 13. This means that the position detectionprocess of modulated SYNC frame data 106 can be simplified.

At the same time, the positions of “SY1” and “SY2” are symmetric andreversed before and after the boundary of segmentation. That is, “SY1”is present immediately before modulated SYNC frame data 106-2, and “SY2”that replaces “SY1” is present immediately before modulated SYNC framedata 106-15 located at a corresponding symmetric position. Also, “SY2”is present immediately before modulated SYNC frame data 106-11, and“SY1” that replaces “SY2” is present in turn immediately beforemodulated SYNC frame data 106-24 located at a corresponding symmetricposition.

In this way, when a physical sector is segmented into two blocks, andallocations before and after the boundary of segmentation are checked,“SY0” are allocated at symmetric positions before and after the boundaryof segmentation, and “SY1” and “SY2” are allocated at symmetric butreversed positions before and after the boundary of segmentation. Withthis allocation, since only three different codes “SY0”, “SY1”, and“SY2” are allocated, the position of modulated SYNC frame data 106,which is currently being reproduced can be detected by examining thecontinuous allocation order of SYNC codes 110.

A method of determining the position of data which is currently beingreproduced in a physical sector using a sequence of a plurality ofpieces of information before and after a plurality of SYNC codes 110,which are allocated based on the SYNC code allocation method shown inFIG. 23, will be described below using FIGS. 24 and 30. Note that FIGS.25 to 29 are flow charts for explaining examples of the operations ofthe apparatus shown in FIGS. 3 and 4, but they will be described later.

Output data (FIG. 24) of the Viterbi decoder 156 (see FIG. 4) istransferred to the SYNC code position extractor (or detector) 145 (stepST51), which detects the position of a SYNC code 110 from that data.That is, a SYNC position detection code detector 182 which comprises acomparator detects the position of a SYNC position detection code 121 bya pattern matching method (step ST52).

After that, information of the detected SYNC code 110 is sequentiallysaved in a memory 175 via the controller 143, as shown in FIG. 24. Thatis, a SYNC frame position identification code content identificationunit 185 extracts information of a SYNC frame position identificationcode 123 using the detection timing of step ST52, and extraction historyinformation is recorded in the memory 175 via the controller 143 (stepST53).

If the position of the SYNC code 110 can be detected, only modulatedSYNC frame data 106 in the data output from the Viterbi decoder 156 canbe extracted and transferred to the shift register circuit 170. That is,only the modulated SYNC frame data 106 is extracted using the timing ofstep ST52, and is transferred to the shift register circuit 170 to delayand adjust the timing (step ST54).

The controller 143 then reads out history information of SYNC codes 110,which is recorded in the memory 175, and identifies the order in whichSYNC frame position identification codes appear (step ST55). Then, theposition of the modulated SYNC frame data 106, which is temporarilysaved in the shift register circuit 170, in a physical sector, isdetected (step ST56). That is, the controller 143 determines theposition of the modulated SYNC frame data 106, which is transferred tothe shift register circuit 170, in a physical sector, from data whichappear in an order shown in, e.g., FIG. 23, on the basis of theidentified order in which SYNC frame position identification codesappear.

The modulated SYNC frame data 106 which is transferred to the shiftregister circuit 170 is transferred to the demodulation circuit 152 tostart demodulation as needed (step ST57).

For example, as shown in FIG. 24, if a sequence of SYNC codes 110, whichis saved in the memory 175 is “SY0→SY2→SY1”, it is determined that“modulated SYNC frame data 106-6” is present immediately after “SY0”; ifit is “SY0→SY0→SY1”, it is determined that “modulated SYNC frame data106-0” is present immediately after “SY0”.

When the position in a physical sector is determined in this way, and itis confirmed that modulated SYNC frame data 106 at a desired position isinput to the shift register circuit 170, that data is transferred to thedemodulation circuit 152 to start demodulation (step ST57).

FIG. 25 is a flow chart for explaining a data conversion process uponadopting the SYNC codes shown in FIGS. 11 and 12.

In step ST1, the interface 142 receives logical sector information 103to be recorded. In step ST2, the Data ID generator 165 generates Data IDinformation and IED information for each sector. In step ST3, the DataID, IED, CPR_MAI, EDC appending unit 168 generates the data structureshown in portion c in FIG. 1 or portion c in FIG. 5.

Furthermore, in step ST4 the scramble circuit 157 scrambles the logicalsector information 103. In step ST5, the ECC encoding circuit 161 formsECC blocks with the structure shown in FIGS. 5, 6, and 7.

In step ST6, a physical sector that forms each ECC block generated inthe ECC encoding circuit 161 is segmented into 26 or 13 SYNC frame data105, as shown in portion d in FIG. 1.

In step ST8, the modulation circuit 151 modulates each SYNC frame data105, and transfers the modulated data to a temporary memory 139.

(1) Upon modulation, the DSV value calculator 148 calculates a DSV valueas needed, selects a table used in modulation from the modulationconversion table memory 153 on the basis of that value, and transfersthat conversion table selection information 192 to a conversion tableselection information memory 133 that stores a conversion table usedupon modulation.

(2) At the same time, of DSV value information 191 calculated uponmodulation, a difference for each SYNC frame data 105 is transferred toa DSV difference history memory 131 that stores a difference for eachSYNC frame data 105.

In step ST9, a conversion table selection code generator 134 forgenerating a conversion table selection code upon modulation sets aconversion table selection code 122 upon conversion on the basis of thedata transferred from the conversion table selection information memory133. The conversion table selection code 122 forms a pattern 129, whichintegrates and is commonly used as a conversion table selection codeupon modulation, SYNC frame position identification code, and DCsuppression polarity inversion pattern.

In step ST10, a SYNC position detection code generator 136 generates aSYNC position detection code 121.

In step ST11, a DC suppression polarity inversion pattern determinationunit 132 sets a DC suppression polarity inversion pattern 124 on thebasis of the DSV calculation result (the output from a DSV valuecalculator 149) for data which has been mixed by a recording data mixingunit 138 and is to be recorded by the information recording/reproducingunit 141, and the output result from a DSV difference history memory 131for each SYNC frame data 105. The DC suppression polarity inversionpattern 124 is a code that forms the pattern 129, which integrates andis commonly used as a conversion table selection code upon modulation,SYNC frame position identification code, and DC suppression polarityinversion pattern.

In step ST12, a SYNC frame position identification code generator 135generates a SYNC frame position identification code 123. The SYNC frameposition identification code 123 is a code that forms the pattern 129,which integrates and is commonly used as a conversion table selectioncode upon modulation, SYNC frame position identification code, and DCsuppression polarity inversion pattern.

In step ST13, a SYNC code 110 generator 137 generates a SYNC code 110 bymixing data generated in steps ST9 to ST12.

In step ST14, the recording data mixing unit 138 mixes the datagenerated by the SYNC code 110 generator 137 and data recorded in themodulated data temporary memory 139 to generate the data structure shownin portion e of FIG. 2.

In step ST15, the data generated in step ST14 is transferred to theinformation recording/reproducing unit 141, which transfers that data tothe information storage medium 9. Also, the DSV value calculator 149calculates the DSV value of that data and transfers the value to the DCsuppression polarity inversion pattern determination unit 132, asneeded.

FIG. 26 is a flow chart for explaining a data conversion process uponadopting the SYNC codes shown in FIGS. 13 to 18.

In step ST1, the interface 142 receives logical sector information 103to be recorded. In step ST2, the Data ID generator 165 generates Data IDinformation and IED information for each sector. In step ST3, the DataID, IED, CPR_MAI, EDC appending unit 168 generates the data structureshown in portion c in FIG. 1 or portion c in FIG. 5.

In step ST4, the scramble circuit 157 scrambles the logical sectorinformation 103. In step ST5, the ECC encoding circuit 161 forms ECCblocks with the structure shown in portion c in FIG. 5 and portions hand i in FIGS. 6 and 7.

In step ST6, a physical sector that forms each ECC block generated inthe ECC encoding circuit 161 is segmented into 26 or 13 SYNC frame data105, as shown in portion d in FIG. 1.

In step ST7, the SYNC frame position identification code generator 136generates a SYNC frame position identification code corresponding to theposition of each modulated SYNC frame data 106 in one physical sector,as shown in portion e in FIG. 2. This SYNC frame position identificationcode is allocated at the head of each SYNC frame data 105 in portion din FIG. 1 in the modulation circuit 151.

In step ST8, the modulation circuit 151 executes a modulation process aswell as the SYNC frame position identification code which is allocatedat the head of each SYNC frame data 105.

(1) Upon modulation, the DSV value calculator 148 calculates a DSV valueas needed, selects a table used in modulation from the conversion tablememory 153 that stores conversion tables to be used in modulation on thebasis of that value, and transfers that conversion table selectioninformation 192 to the memory 133 as conversion table selectioninformation indicating a table adopted upon modulation.

(2) At the same time, of DSV value information 191 calculated uponmodulation, a difference for each SYNC frame data 105 is transferred tothe DSV difference history memory 131 that stores a difference for eachSYNC frame data 105.

In step ST9, the conversion table selection code generator 134 forgenerating a conversion table selection code upon modulation sets aconversion table selection code 122 upon conversion on the basis of thedata transferred from the conversion table selection information memory133.

In step ST10, the SYNC position detection code generator 136 generates aSYNC position detection code 121.

In step ST11, the DC suppression polarity inversion patterndetermination unit 132 sets a DC suppression polarity inversion pattern124 on the basis of the DSV calculation result (the output from the DSVvalue calculator 149) for data which has been mixed by the recordingdata mixing unit 138 and is to be recorded by the informationrecording/reproducing unit 141, and the output result from the DSVdifference history memory 131 for each SYNC frame data 105.

In step ST13, the SYNC code 110 generator 137 generates a SYNC code 110by mixing data generated in steps ST9 to ST11.

In step ST14, the recording data mixing unit 138 mixes the datagenerated by the SYNC code 110 generator 137 and data recorded in themodulated data temporary memory 139 to generate the data structure shownin portion e of FIG. 2.

In step ST15, the data generated in step ST14 is transferred to theinformation recording/reproducing unit 141, which transfers that data tothe information storage medium 9. Also, the DSV value calculator 149calculates the DSV value of that data and transfers the value to the DCsuppression polarity inversion pattern determination unit 132, asneeded.

FIG. 27 is a flow chart for explaining a data conversion process uponsimply reproducing information by the apparatus of the presentinvention.

In step ST21, the interface 142 receives an instruction of a range to bereproduced from the information storage medium 9. In step ST22, theinformation recording/reproduction unit 141 reproduces data thatincludes both SYNC codes 110 and modulated SYNC frame data 106 shown inportion e in FIG. 2, and directly transfers reproduced data to a shiftregister circuit 181. In step ST23, a SYNC position detection codedetector 182 which comprises a comparator circuit detects the transfertiming of a SYNC position detection code 121.

In step ST24, a variable code transfer unit 183 extracts a conversiontable selection code 122 upon modulation on the basis of the timingdetected in step ST23, and transfers that code to the a modulationconversion table selection code identification unit 183.

In step ST25, the modulation conversion table selection codeidentification unit 183 decodes the conversion table selection code 122to obtain conversion table selection information 196, and transfers thedecoding result to a demodulation conversion table selection/transferunit 189.

In step ST26, an identification unit (for identifying the contents of aSYNC frame position identification code) 185 or 186 in the SYNC codeposition extractor 145 or demodulation circuit 152 reads information ofa SYNC frame position identification code 123 from the data transferredfrom the information recording/reproduction unit 141 on the basis of thetiming detected in step ST23. By the method shown in FIG. 30, theposition of modulated SYNC frame data 106 is determined, and ademodulation process is done using the data transferred in step ST24.

In step ST27, the ECC decoding circuit 162 makes error correction. Instep ST28, the descramble circuit 159 executes a descramble process.

In step ST29, the logical sector information extractor 173 deletes DataID, IED, CPR_MAI, and EDC, and transfers logical sector information 103alone to an external apparatus via the interface 142.

FIG. 28 is a flow chart for explaining the control operation when theSYNC codes shown in FIGS. 11 and 12 are adopted, and access is made to apredetermined position on the information storage medium.

In step ST31, the interface 142 receives an instruction of a range to bereproduced from the information storage medium 9. In step ST32, thecontroller 143 calculates the value of Data ID 1 corresponding to thereproduction start sector on the information storage medium 9 on thebasis of the information received in step ST31.

In step ST33, the controller 143 controls the informationrecording/reproducing unit 141 to start reproduction of information froman approximate reproduction start position on the information storagemedium 9. In step ST34, the information recording/reproduction unit 141reproduces data that includes both SYNC codes 110 and modulated SYNCframe data 106 shown in portion e in FIG. 2, and directly transfersreproduced data to the shift register circuit 181.

In step ST35, the SYNC position detection code detector 182 detects thetransfer timing of a SYNC position detection code 121. In step ST36, themodulation conversion table selection code identification unit 187decodes conversion table selection information 196 using the timingdetected in step ST35, and transfers the decoding result to thedemodulation conversion table selection/transfer unit 189.

In step ST37, information of a SYNC frame position identification code123 present in the variable code transfer unit 183 or a variable codetransfer unit 184 is read using the timing detected in step ST35. By themethod shown in FIG. 30, the position of SYNC frame data 106, which iscurrently being reproduced, in a physical sector is detected, and thatdetection result is transferred to the controller 143.

It is checked in step ST40 if the detected position of SYNC frame datais that of first SYNC frame data 106-1 in a physical sector. If YES instep ST40, Data ID 1-0 and IED 2-0 information present at the headposition of first SYNC frame data 105-0 in a physical sector aretransferred to the Data ID field & IED field extractor 171 using thetiming detected in step ST35 in step ST41. On the other hand, if NO instep ST40, the flow returns to step ST34.

The Data ID field error checker 172 checks in step ST42 if Data ID 1information detected using IDE 2 is free from any errors.

It is determined in step ST43 if Data ID 1 suffers any errors. If YES instep S43, the ECC decoding circuit 162 extracts Data ID 1 after an errorcorrection process in step S44. If Data ID 1 is free from any errors, itis checked in step ST45 if a target track on the information storagemedium 9 is currently being traced. If YES in step ST45, reproduction ofinformation from the information storage medium 9 is started in stepST46. On the other hand, if NO in step ST45, the controller 143calculates a track error amount on the information storage medium 9 onthe basis of the difference between the value of Data ID 1 of thereproduction result, and Data ID 1 of a target reproduction start sectorin step ST47, and the flow returns to step ST33.

FIG. 29 is a flow chart for explaining the control operation when theSYNC codes shown in FIGS. 13 to 18 are adopted, and access is made to apredetermined position on the information storage medium.

In step ST31, the interface 142 receives an instruction of a range to bereproduced from the information storage medium 9. In step ST32, thecontroller 143 calculates the value of Data ID 1 corresponding to thereproduction start sector on the information storage medium 9 on thebasis of the information received in step ST31.

In step ST33, the controller 143 controls the informationrecording/reproducing unit 141 to start reproduction of information froman approximate reproduction start position on the information storagemedium 9.

In step ST34, the information recording/reproduction unit 141 reproducesdata that includes both SYNC codes 110 and modulated SYNC frame data 106shown in portion e in FIG. 2, and directly transfers reproduced data tothe shift register circuit 181.

In step ST35, the SYNC position detection code detector 182 detects thetransfer timing of a SYNC position detection code 121.

In step ST36, the modulation conversion table selection codeidentification unit 187 decodes conversion table selection information196 using the timing detected in step ST35, and transfers the decodingresult to the demodulation conversion table selection/transfer unit 189.

In step ST38, the demodulation circuit 152 demodulates from the head ofmodulated SYNC frame data 106 using the timing detected in step ST35 andthe conversion table selection information 196 obtained in step ST36. Atthis time, demodulation starts from “modulated SYNC frame positionidentification code 125” located at the head of the modulated data field107, as shown in portion (A) in FIG. 13, portion (B) in FIG. 13, andportion (A) in FIG. 14.

In step ST39, the SYNC frame position identification code contentidentification unit 186 decodes the contents of the demodulated SYNCframe position identification code 123, and determines the position ofSYNC frame data 106 by the method shown in FIG. 30.

It is checked in step ST40 if the determined position is that of firstSYNC frame data 106-1 in a physical sector. If NO in step ST40, the flowreturns to step ST34. If YES in step ST40, Data ID 1-0 and IED 2-0information present at the head position of first SYNC frame data 105-0in a physical sector are transferred to the Data ID field & IED fieldextractor 171 using the timing detected in step ST35 (step ST41).

The Data ID field error checker 172 checks in step ST42 if Data ID 1information detected using information of IDE 2 is free from any errors.

It is determined in step ST43 if Data ID 1 suffers any errors. If YES instep S43, the ECC decoding circuit 162 extracts Data ID 1 after an errorcorrection process in step S44. If Data ID 1 is free from any errors, itis checked in step ST45 if a target track on the information storagemedium 9 is currently being traced. If YES in step ST45, reproduction ofinformation from the information storage medium 9 is started (stepST46).

The controller 143 calculates a track error amount on the informationstorage medium 9 on the basis of the difference between the value ofData ID 1 of the reproduction result, and Data ID 1 of a targetreproduction start sector in step ST47.

In the apparatus of the present invention, it is also easy to provide anabnormality detection function such as track errors by monitoring theorder in which SYNC codes appear.

FIG. 31 shows such example. This process can also be implemented by analgorithm provided to the controller 143. In step ST61, the interfacereceives an instruction of a range to be reproduced from an informationstorage medium by an external operation input or control input. Then,access to the reproduction start position on the information storagemedium is executed based on the flow chart shown in FIG. 28 or 29, thusstarting data reproduction (step ST62). Then, seamless reproduction isexecuted according to the sequence shown in FIG. 27 (step ST63). Thecontroller 143 predicts a continuous combination of next SYNC codes 110to be detected (step ST64). History information of SYNC codes 110 isread out by the method according to the flow chart in FIG. 30, and iscompared with the combination predicted in step ST64 (step ST66). As aresult of comparison, if the history information matches the predictedcombination, it is determined that a target track on the informationstorage medium is being traced, and the flow returns to step ST63;otherwise, the flow returns to step ST62.

The present invention will be summarized below.

(1) User information is recorded on an information storage medium infirst recording units (physical sectors 5) in a format after the userinformation is modulated according to the (d, k; m, n) modulation rule.At this time, the present invention is characterized in that a SYNC codeis allocated at least at one position in the first recording unit, andall patterns that can be used as the SYNC code satisfy a condition thatthe number of “1”s included in a series of N channel bits at anarbitrary position (at all positions) is equal to or smaller thanINT[N/(d+1)]. Note that INT[X] is an integer value obtained by droppingdigits after the decimal point of X, and N={(d+1)×INT[9/(d+1)]}+1.

(2) User information is recorded on an information storage medium infirst recording units (physical sectors 5) in a format after the userinformation is modulated according to the (d, k; m, n) modulation rule.At this time, the present invention is characterized in that a SYNC codeis allocated at least at one position in the first recording unit, andat least 66% of all patterns that can be used as the SYNC code satisfy acondition that the number of “1”s included in a series of (N−1) channelbits at an arbitrary position (at all positions) is equal to or smallerthan “INT[(N−1)/(d+1)]−1”. Note that INT[X] is an integer value obtainedby dropping digits after the decimal point of X, andN={(d+1)×INT[9/(d+1)]}+1.

(3) User information is recorded on an information storage medium infirst recording units (physical sectors 5) in a format after the userinformation is modulated according to the (d, k; m, n) modulation rule.At this time, the present invention is characterized in that a conditionof d=1 is met, a SYNC code is allocated at least at one position in thefirst recording unit, and all patterns that can be used as the SYNC codesatisfy a condition that the number of “1”s included in a series of 9channel bits at an arbitrary position (at all positions) in the SYNCcode is equal to or smaller than 4.

(4) User information is recorded on an information storage medium infirst recording units (physical sectors 5) in a format after the userinformation is modulated according to the (d, k; m, n) modulation rule.At this time, the present invention is characterized in that a conditionof d=1 is met, a SYNC code is allocated at least at one position in thefirst recording unit, and at least 66% of all patterns that can be usedas the SYNC code satisfy a condition that the number of “1”s included ina series of 8 channel bits at an arbitrary position (at all positions)in the SYNC code is equal to or smaller than 3.

By satisfying the conditions in (1) to (4), the frequency of occurrenceof the densest patterns in a SYNC code can be reduced, and that of bitshift errors in the SYNC code position can be reduced, thus improvingthe reliability of a reproduced signal from the SYNC code. That is, as aresult of devising the SYNC code pattern by the aforementioned method,the reproduced signal amplitude value range from the SYNC code can bebroadened, the reference clock extraction (carrier reproduction)prediction based on “SYNC detection” using a reproduced from the SYNCcode position can be improved, and the frequency of occurrence of timingerrors (bit shifts) of a reference clock at the SYNC code position canbe reduced, thus improving the detection precision of the SYNC code.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. An information recording apparatus for recording information on aninformation storage medium, comprising: a generator generatingpredetermined data; and a recorder recording the predetermined data,wherein a part of the predetermined data is modulated according to a (d,k; m, n) modulation rule, the (d, k; m, n) modulation rule modulatesm-bit source data into n-channel bit data, so that modulated channel bitpatterns satisfy conditions that a minimum of d pieces of 0ssuccessively arranged and a maximum of k pieces 0s successivelyarranged, the predetermined data includes a plurality of SYNC codes inpredetermined recording units, a number of 1s included in apredetermined number of a series of channel bits at an arbitraryposition in the SYNC code is not more than a half the predeterminednumber, each of the plurality of SYNC codes includes a fixed code and avariable code, wherein the fixed code includes k or more sequences of 0ssuccessively arranged and d+1 sequences of 0s successively arranged,wherein the variable code is one of a first pattern (SY0), a secondpattern (SY1), a third pattern (SY2), and a fourth pattern (SY3),wherein the variable code of the lead of the SYNC codes in thepredetermined recording units is the first pattern, combinations of thevariable codes of three successive SYNC codes in the predeterminedrecording units are different from one another, and the SYNC code iscomprised of 24 channel bits, SYNC frame data subsequent to the SYNCcode is comprised of 1092 channel bits, four types of SYNC codesincluding the first pattern, the second pattern, the third pattern, andthe fourth pattern, respectively, are defined, each of the predeterminedrecording units is called one sector, and the first pattern and thesecond pattern are sequentially arranged from an initial position ofsaid one sector.
 2. An apparatus according to claim 1, wherein allpatterns contained in the SYNC code satisfy a condition that a number of1s included in a series of N channel bits is not more than INT[N/(d+1)]where INT[X] is an integer value obtained by dropping digits after thedecimal point of X, and N is given by N={(d+1).times.INT[9/(d+1)]}+1. 3.An apparatus according to claim 1, wherein not less than 66% of patternscontained in the SYNC code satisfy a condition that a number of 1sincluded in a series of (N−1) channel bits is not more thanINT[(N−1)/(d+1)]−1 where INT[X] is an integer value obtained by droppingdigits after the decimal point of X, and N is given byN={(d+1).times.INT[9/(d+1)]}+1.
 4. An information reproduction apparatusfor reproducing information from an information storage medium,comprising: a reader reading out predetermined data from the informationstorage medium, and a reproducer reproducing various data on the basisof a SYNC code contained in the predetermined data, wherein a part ofthe predetermined data is modulated according to a (d, k; m, n)modulation rule, the (d, k; m, n) modulation rule modulates m-bit sourcedata into n-channel bit data, so that modulated channel bit patternssatisfy conditions that a minimum of d pieces of 0s successivelyarranged and a maximum of k pieces of 0s successively arranged, thepredetermined data includes plurality of SYNC codes in predeterminedrecording units, a number of 1s included in a predetermined number of aseries of channel bits at an arbitrary position in the SYNC code is notmore than a half the predetermined number, each of the plurality of SYNCcodes includes a fixed code and a variable code, wherein the fixed codeincludes k or more sequences of 0s successively arranged and d+1sequences of 0s successively arranged, wherein the variable code is oneof a first pattern (SY0), a second pattern (SY1), a third pattern (SY2),and a fourth pattern (SY3), combinations of the variable codes of threesuccessive SYNC codes in the predetermined recording units are differentfrom one another, and the SYNC code is comprised of 24 channel bits,SYNC frame data subsequent to the SYNC code is comprised of 1092 channelbits, four types of SYNC codes including the first pattern, the secondpattern, the third pattern, and the fourth pattern, respectively, aredefined, each of the predetermined recording units is called one sector,and the first pattern and the second pattern are sequentially arrangedfrom an initial position of said one sector.
 5. An apparatus accordingto claim 4, wherein all patterns contained in the SYNC code satisfy acondition that a number of is included in a series of N channel bits isnot more than INT[N/(d+1)] where INT[X] is an integer value obtained bydropping digits after the decimal point of X, and N is given byN={(d+1).times.INT[9/(d+1)]}+1.
 6. An apparatus according to claim 4,wherein not less than 66% of patterns contained in the SYNC code satisfya condition that a number of is included in a series of (N−1) channelbits is not more than INT[(N−1)/(d+1)]−1 where INT[X] is an integervalue obtained by dropping digits after the decimal point of X, and N isgiven by N={(d+1).times.INT[9/(d+1)]}+1.
 7. An information recordingmethod for recording information on an information storage medium,comprising: generating predetermined data; and recording thepredetermined data, wherein a part of the predetermined data ismodulated according to a (d, k; m, n) modulation rule, the (d, k; m, n)modulation rule modulates m-bit source data into n-channel bit data, sothat modulated channel bit patterns satisfy conditions that a minimum ofd pieces of 0s successively arranged and a maximum of k pieces 0ssuccessively arranged, the predetermined data includes a plurality ofSYNC codes in predetermined recording units, a number of 1s included ina predetermined number of a series of channel bits at an arbitraryposition in the SYNC code is not more than a half the predeterminednumber, each of the plurality of SYNC codes includes a fixed code and avariable code, wherein the fixed code includes k or more sequences of 0ssuccessively arranged and d+1 sequences of 0s successively arranged,wherein the variable code is one of a first pattern (SY0), a secondpattern (SY1), a third pattern (SY2), and a fourth pattern (SY3),wherein the variable code of the lead of the SYNC codes in thepredetermined recording units is the first pattern, combinations of thevariable codes of three successive SYNC codes in the predeterminedrecording units are different from one another, and the SYNC code iscomprised of 24 channel bits, SYNC frame data subsequent to the SYNCcode is comprised of 1092 channel bits, four types of SYNC codesincluding the first pattern, the second pattern, the third pattern, andthe fourth pattern, respectively, are defined, each of the predeterminedrecording units is called one sector, and the first pattern and thesecond pattern are sequentially arranged from an initial position ofsaid one sector.
 8. A method according to claim 7, wherein all patternscontained in the SYNC code satisfy a condition that a number of 1sincluded in a series of N channel bits is not more than INT[N/(d+1)]where INT[X] is an integer value obtained by dropping digits after thedecimal point of X, and N is given by N={(d+1).times.INT[9/(d+1)]}+1. 9.A method according to claim 7, wherein not less than 66% of patternscontained in the SYNC code satisfy a condition that a number of 1sincluded in a series of (N−1) channel bits is not more thanINT[(N−1)/(d+1)]−1 where INT[X] is an integer value obtained by droppingdigits after the decimal point of X, and N is given byN={(d+1).times.INT[9/(d+1)]}+1.
 10. An information reproduction methodfor reproducing information from an information storage medium,comprising: reading out predetermined data from the information storagemedium, and reproducing various data on the basis of a SYNC codecontained in the predetermined data, wherein a part of the predetermineddata is modulated according to a (d, k; m, n) modulation rule, the (d,k; m, n) modulation rule modulates m-bit source data into n-channel bitdata, so that modulated channel bit patterns satisfy conditions that aminimum of d pieces of 0s successively arranged and a maximum of kpieces of 0s successively arranged, the predetermined data includesplurality of SYNC codes in predetermined recording units, a number of 1sincluded in a predetermined number of a series of channel bits at anarbitrary position in the SYNC code is not more than a half thepredetermined number, each of the plurality of SYNC codes includes afixed code and a variable code, wherein the fixed code includes k ormore sequences of 0s successively arranged and d+1 sequences of 0ssuccessively arranged, wherein the variable code is one of a firstpattern (SY0), a second pattern (SY1), a third pattern (SY2), and afourth pattern (SY3), wherein the variable code of the lead of the SYNCcodes in the predetermined recording units is the first pattern,combinations of the variable codes of three successive SYNC codes in thepredetermined recording units are different from one another, and theSYNC code is comprised of 24 channel bits, SYNC frame data subsequent tothe SYNC code is comprised of 1092 channel bits, four types of SYNCcodes including the first pattern, the second pattern, the thirdpattern, and the fourth pattern, respectively, are defined, each of thepredetermined recording units is called one sector, and the firstpattern and the second pattern are sequentially arranged from an initialposition of said one sector.
 11. A method according to claim 10, whereinall patterns contained in the SYNC code satisfy a condition that anumber of 1s included in a series of N channel bits is not more thanINT[N/(d+1)] where INT[X] is an integer value obtained by droppingdigits after the decimal point of X, and N is given byN={(d+1).times.INT[9/(d+1)]}+1.
 12. A method according to claim 10,wherein not less than 66% of patterns contained in the SYNC code satisfya condition that a number of 1s included in a series of (N−1) channelbits is not more than INT[(N−1)/(d+1)]−1 where INT[X] is an integervalue obtained by dropping digits after the decimal point of X, and N isgiven by N={(d+1).times.INT[9/(d+1)]}+1.
 13. An information recordingmethod for recording information on an information storage medium,comprising: generating predetermined data; and recording thepredetermined data, wherein a part of the predetermined data ismodulated according to a (d, k; m, n) modulation rule, the (d, k; m, n)modulation rule modulates m-bit source data into n-channel bit data, sothat modulated channel bit patterns satisfy conditions that a minimum ofd pieces of 0s successively arranged and a maximum of k pieces 0ssuccessively arranged, and the predetermined data includes a pluralityof SYNC codes in predetermined recording units.